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MSI Z690 Unify-X Thread

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Figured we might as well get some threads going for boards.


U.S. Support Page for MSI Drivers: 


The MEG Z690 UNIFY-X ATX motherboard features Direct 19+2 Phases and 105A SPS Power Solution, 4 x latest DDR5 DIMMs (dual channel) with Memory Boost architecture (6800+ MHz/OC), and dual...



Check these links for BETA BIOS releases. Due to MSI not having much (or any..) community involvement, I frequently check these to see if there's any updated BETA releases on it:


Beta/MP - Google Drive

File sharing (weiyun.com)

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My current setup:



Z690 Unify-X

Kingston 6400CL32 Hynix M-Die


Sticks are watercooled w/ IceManCooler heatspreaders+1DPC block


Due to certain Z690 Unify-X boards having an issue with their ChA slot (somewhat similar to the ASUS Z690 APEX issue, though the Unify-X has this issue at much higher frequencies), I can't get 7200 stable. My ChA slot is stuck at 7000 for stability, so I've spent time bringing timings down significantly, resulting in a really tight setup! Watercooling allowed really low tRFC. I can run tREFI maxed out, but I use 131072 for 24/7.


CPU SA: 1.050v

CPU VDDQ: 1.365v

CPU VDD2: 1.400v

DRAM VDD: 1.550v

DRAM VDDQ: 1.500v

DRAM VPP: 1.800v



Edited by acoustic
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Training profile for other members to test; I've had success with this profile as well as 2-3 others that have tested it. No guarantees, but it may help you find stability at higher frequencies/borderline stability scenarios. You can try it on any BIOS, but I feel it's most useful on A9/A91. I focused on DFE/Rx Equalization training, something that the A9/A91 BIOS seems to like messing with. Take a look at your Rx Equalization value, as well as your ODT read/write delays. You may notice they have values now, rather than the typical zero.


Rx Equalization is an excellent aid in stabilizing higher frequencies, however it does come at the cost of power consumption. If you see higher temps, let me know.


You may have to manually enter RTLs, but from my testing, I fixed this issue. Earlier revisions would cause no display initialization after POST with RTLs on Auto; you'd just sit at A6 post-code. Seems to be working fine now, though.


Enable the following:


DCC Optimize

SenseAmp Offset Training

Early DIMM DFE Training

CMD CTL Drive Strength / Tx Equalization

CMD CTL CLK Slew Rate Training (unless you manually enter ODTs, then disable)

DIMM ODT Training (unless you manually enter ODTs, then disable)

Read Equalization Training

DIMM DFE Training

Read ODT Training (unless you manually enter ODTs, then disable)

Write Slew Rate Training (unless you manually enter ODTs, then disable)

Round Trip Latency


Disable the following:


DIMM SPD Alias Test

Margin Limit Check

Memory Test

Edited by acoustic
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  • 3 weeks later...



New BETA, A91U1, with apparently some improved high frequency memory stability, along with fixing Ring Downbin issues introduced with the A91/A9 BIOS releases. Now, we can set Ring Downbin to enable/disable, as well as set a Ring Min Ratio, so we can leave Downbin enabled and alter how low it goes. This has been a feature many have been asking for, so good to finally see it added.

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