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Some AMD 5600X and 5800X CPUs come with two CCDs


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The creator of CTR and DRAM Calculator for Ryzen has found that some Ryzen 5 5600X and Ryzen 7 5800X processors feature a dual CCD design instead of a single CCD. For now, there isn’t an easy way to check if one of these processors has one or two CCDs, but once CTR 2.0 releases, that will change

Source:https://www.kitguru.net/components/cpu/joao-silva/some-amd-ryzen-5-5600x-and-ryzen-7-5800x-cpus-come-with-two-ccds/

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8 hours ago, ENTERPRISE said:

Source:https://www.kitguru.net/components/cpu/joao-silva/some-amd-ryzen-5-5600x-and-ryzen-7-5800x-cpus-come-with-two-ccds/

Hmm don't like the sound of that.

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7 hours ago, Sir Beregond said:

Hmm don't like the sound of that.

In what respect ? Just curious.

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5 hours ago, ENTERPRISE said:

In what respect ? Just curious.

You know, I re-read the article fresh today and I guess I am fine. I suppose the bin could be worse, but otherwise its still just one of the CCD's disabled from a failed 5900X right? My initial concern was a potential situation where 5600X and 5800X were running some cores in both CCD's. I don't know where that idea came from. Concerns withdrawn. :)

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1 hour ago, Sir Beregond said:

You know, I re-read the article fresh today and I guess I am fine. I suppose the bin could be worse, but otherwise its still just one of the CCD's disabled from a failed 5900X right? My initial concern was a potential situation where 5600X and 5800X were running some cores in both CCD's. I don't know where that idea came from. Concerns withdrawn. :)

Ha, that is fair enough. I would share concerns if they had enabled cores across a 2 CCD's with one of the CCD's being of a not so stable nature. It will be interesting if there is a way of "Unlocking" the second CCD as from the article it is active but asleep so to speak. Of course if you were able to re-activate it, I would assume you would have to manually tweak that CCD to disable certain cores or lower the core clock in order to reach stability.

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This is not exactly the same, but still sheds some light on enabling (and disabling) chiplets. The two-chiplet 2950X (16C/32T) Threadripper in one of my machines has a unique option the four-chiplet 2990WX (32C/64T) doesn't have: default UMA and non-default NUMA modes. While the latter doesn't exactly turn one of the two chiplets completely on or off, it still shifts the priority heavily to one chiplet and its associated RAM with much tighter latencies, and higher core use profiles.

 

Case in point is Cyberpunk 2077 below (fyi, run at 4K which stresses the CPU relatively less than for example 1080p), with same settings and scenes. End result is higher performance in some apps, including for example 3DM Port Royal. Point is: It's good to be able to choose chiplet engagement and priority. 

 

uma_numa3.thumb.jpg.3fb89c24733820b6bd83c344e3e41d97.jpg

  

Of course with the OP, I'm now wondering whether the two extra 'dummy' chiplets in the 2950X are actually just real chiplets that didn't make the binning cut, slumbering away underneath the IHS for the past two years...? 

  

  

 

Edited by J7SC_Orion

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6 hours ago, J7SC_Orion said:

This is not exactly the same, but still sheds some light on enabling (and disabling) chiplets. The two-chiplet 2950X (16C/32T) Threadripper in one of my machines has a unique option the four-chiplet 2990WX (32C/64T) doesn't have: default UMA and non-default NUMA modes. While the latter doesn't exactly turn one of the two chiplets completely on or off, it still shifts the priority heavily to one chiplet and its associated RAM with much tighter latencies, and higher core use profiles.

 

Case in point is Cyberpunk 2077 below (fyi, run at 4K which stresses the CPU relatively less than for example 1080p), with same settings and scenes. End result is higher performance in some apps, including for example 3DM Port Royal. Point is: It's good to be able to choose chiplet engagement and priority. 

 

uma_numa3.thumb.jpg.3fb89c24733820b6bd83c344e3e41d97.jpg

  

Of course with the OP, I'm now wondering whether the two extra 'dummy' chiplets in the 2950X are actually just real chiplets that didn't make the binning cut, slumbering away underneath the IHS for the past two years...? 

  

  

 

The UMA and NUMA style thinking is possibly what AMD has done. Used that same sort of Logic to put the 2nd CCD to sleep. One would imagine this is done via microcode on the BIOS which instructs the system to fully ignore the 2nd CCD. If that is the case then someone clever can modify the BIOS to wake the 2nd CCD. Now results would vary, just enabling the 2nd CCD could result in constant crash/post issues depending on how poor that CCD is.

 

However if you are lucky, as I say you may either need to disable certain cores or down lock them.

 

Will be interesting to see what @1usmus will find.

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