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TSMC adopts nanosheet transistors for its 2nm fabrication process


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Nanosheets are a sort of gate-all-around field-effect transistor (GAAFET) in which a gate surrounds floating transistor fins. TSMC will deploy nanosheets in their 2nm process, which will go into production in 2025.


As a preview for its annual technology symposium, which will be conducted in numerous global locations in the coming months, TSMC briefed a small group of press reporters on its roadmap for the next several years. According to Kevin Zhang, TSMC vice president of Business Development, the world's leading chip foundry is studying additional process technologies such as complementary FET (CFET) to follow nanosheet.


CFET is an advancement in nanosheet technology. In order to obtain increased transistor density, it stacks both n–type and p–type devices on top of each other. TSMC is looking for innovative transistor layouts that can aid in the reduction of energy usage in HPC applications such as data centers, which contribute considerably to global warming.


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