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Intel Official Lunar Lake Reveal

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Intel unveiled details of its upcoming Lunar Lake architecture at the Intel Tech Tour 2023 in Taipei, Taiwan, signaling a strategic pivot in design and manufacturing ahead of its Q3 launch. Lunar Lake, primarily targeting mobile platforms, integrates significant enhancements across its components and is expected to power high-performance laptops. The architecture introduces improved Efficiency cores (E-cores) and Performance cores (P-cores). The E-cores in the Skymont architecture showcase IPC gains of 38% and 68%, while the Lion Cove P-cores achieve a 14% IPC gain. Intel has also enhanced its integrated GPU, the Xe2, which promises a 50% increase in performance, aligning with advanced graphical demands.


Intel's incorporation of a Neural Processing Unit (NPU) in Lunar Lake is notable, offering 48 TOPS of AI performance, exceeding Microsoft's next-gen AI PC requirement of 40 TOPS. The combined capabilities of the CPU and iGPU bring the total AI performance to 120 TOPS.


Lunar Lake employs a new design methodology prioritizing power efficiency, which will serve as the foundation for future Intel products, including Arrow Lake and Panther Lake. This approach is crucial for Intel's competitiveness against AMD, Apple, and Qualcomm in the laptop market.


In a strategic manufacturing decision, Intel partnered with TSMC to utilize its 3nm N3B process node for the compute tile, which houses the CPU, GPU, and NPU, and the N6 node for the platform controller tile, managing external I/O interfaces. The passive 22FFL Foveros base tile, fabricated by Intel, supports inter-tile communication.


This shift to TSMC's nodes acknowledges previous delays in Intel’s manufacturing capabilities. Intel has designed these architectures for easy portability across different process nodes, indicating potential future shifts back to Intel’s manufacturing nodes.


Lunar Lake's design advancements extend beyond mobile chips. Intel plans to integrate these microarchitectures into its desktop Arrow Lake processors and Xeon 6 series. However, Lunar Lake chips will omit hyperthreading from the P-cores, a move aimed at enhancing efficiency and reducing chip surface area. This decision reflects Intel's strategy to optimize core performance without hyperthreading, leveraging the efficiency of the E-cores introduced in the Alder Lake architecture.


The Lunar Lake chip includes four P-cores and four E-cores in the top-tier SKU. It features a dual-logic-tile configuration, comprising a compute tile and a platform controller tile connected to a base Foveros tile. This assembly uses a 25-micron bump pitch for improved interconnect density, reducing power consumption and enhancing communication pathways between components.


Memory integration in Lunar Lake includes two stacks of LPDDR5X-8500 memory, available in 16GB or 32GB configurations, directly on the chip package to decrease latency and save board space while reducing the memory PHY’s power consumption by 40%.




Seems like Intel is shaking things up. Ram on the chip, will be interesting to see how that performs. 



CPU: 5800x
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I'm rather intrigued to see how Arrow Lake turns out with this major shift in architecture / packaging. My biggest concern would be if they continue to insane power draw of the previous gen to achieve said performance, or if they actually end up not only competitive in performance but power / efficiency too.



CPU: AMD Ryzen 9 5900X
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RAM: G.Skill Trident Z Neo 32GB DDR4-3600 (@ 3733 CL14)
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